Detailed Design Flow for Partial Reconfiguration
نویسنده
چکیده
With the rapid development of VLSI Technology, FPGA exposed many limitations at the area, speed, power, and chip capacity. Newer Xilinx FPGAs (few Spartan & Virtex series) provides the possibility to be reconfigured by Dynamic Partial Reconfiguration (DPR) technique. DPR is defined as the ability of a single system to get reconfigured to perform multiple applications. The main contribution of this paper is in proposing a complete design flow of the partial reconfiguration technology which analyzed on Xilinx Virtex -5 ML507 Board. It is shown in the experiment that flexibility of the system was improved greatly by the dynamic partial reconfiguration.
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تاریخ انتشار 2014